平行式 NAND 系統功率計算器

Approximating NAND average power consumption for a system is a useful exercise to help determine NAND device power consumption’s role in a system’s power budget and how to potential optimize that budget for NAND operations. This tool provides an estimate of NAND current/power consumption per host channel and system NAND power consumption for a NAND Read-Program-Erase-Idle-Standby workload.

The audience for this calculator is a user looking to approximate NAND power consumption who understands the NAND devices used, type of NAND operations used, and their respective current (Icc) specifications. The user of this calculator is expected to know the physical and operational characteristics of the system such as (but not limited to) NAND host data input/output interface speed, system parallel use of the NAND LUNs/die, voltage supply levels to the NAND, NAND Read-Program-Erase-Idle-Standby workloads, capacitance of board traces - controller DQ bus - and other physical system elements.

Micron products are warranted only to meet Micron’s data sheet specifications. This tool, Micron products, programs and specifications are subject to change without notice. 所有提供之資訊皆以「現況」為基準，不提供任何形式的保固。Additional verification of calculation outputs is recommended to ensure accuracy.

Enter a value for each item

Parallel NAND device with DQ[7:0] or DQ[15:0] bus being used by the host system (1 = DQ[7:0] NAND device used, 2 = DQ[15:0] NAND device used)

This value should be either 1 or 2

Number of NAND DQ[7:0] or NAND DQ[15:0] host channels

Number of NAND LUNs/die per host channel

Number of NAND CE# signal per host channel (assumed to be evenly distributed by # of NAND LUNs/die per host channel)

Host NAND interface speed in MT/s (e.g. 50 for 50MT/s, 800 for 800MT/s, etc.)

Capacitive loading of host system per NAND DQ[7:0] or NAND DQ[15:0] channel in pF not including NAND devices Learn More

Host system supplied NAND Vcc in Volts

Host system supplied NAND Vccq in Volts

Host system supplied NAND Vpp in Volts (if used)

Number of NAND LUNs/die per host NAND DQ[7:0] or NAND DQ[15:0] channel are busy (SR5 = 0) with the most used Read operation at the same time Learn More

This value should not be greater than the value used in the 'Number of NAND LUNs/die per host channel' row

Number of NAND LUNs/die per host NAND DQ[7:0] or NAND DQ[15:0] channel are busy (SR5 = 0) with the 2nd most used Read operation at the same time Learn More

This value should not be greater than the value used in the 'Number of NAND LUNs/die per host channel' row

Number of NAND LUNs/die per host NAND DQ[7:0] or NAND [15:0] channel are busy (SR5 = 0) with the most used Program operation at the same time Learn More

This value should not be greater than the value used in the 'Number of NAND LUNs/die per host channel' row

Number of NAND LUNs/die per host NAND DQ[7:0] or NAND DQ[15:0] channel that are busy (SR5 = 0) with the most used Erase operation at the same time Learn More

This value should not be greater than the value used in the 'Number of NAND LUNs/die per host channel' row

NAND mode of operation used by the host system (1 = Async mode, 2 = NV-DDR/NV-DDR2/NV-DDR3/NV-LPDDR4 mode)

This value should be either 1 or 2

Capacitance of the NAND package DQ[7:0] or DQ[15:0] channel in pF

Number of NAND package DQ[7:0] or DQ[15:0] channels shorted/shared per host NAND DQ[7:0] or DQ[15:0] channel Learn More

NAND array Read current for most used Read operation (e.g. NAND Icc1 specification) in mA Learn More

NAND array Read current for 2nd most used Read operation (e.g. NAND Icc1 specification) in mA Learn More

NAND Program current for most used Program operation (e.g. NAND Icc2 specification) in mA Learn More

NAND Erase current for most used Erase operation (e.g. NAND Icc3 specificaiton) in mA Learn More

NAND Vpp current for most used Read operations (e.g. NAND IPPA1 specification, if used) in mA

NAND Vpp current for 2nd most used Read operations (e.g. NAND IPPA1 specification, if used) in mA

NAND Vpp current for Program operations (e.g. NAND IPPA2 specification, if used) in mA

NAND Vpp current for Erase operations (e.g. NAND IPPA3 specification, if used) in mA

NAND standby current (e.g. NAND Isb and Isbq specification) in µA

NAND Idle current (e.g. Icc5 and Iccq5 specifications) in mA

NAND data output current at the NAND interface speed being used (e.g. NAND Icc4r and Iccq4r specificaiton) in mA

NAND data input current at the NAND interface speed being used (e.g. NAND Icc4w and Iccq4w specification) in mA

NAND array Read current on Vccq rail (e.g. NAND Iccq1 specification) in mA

NAND array Program current on Vccq rail (e.g. NAND Iccq2 specification) in mA

NAND array Erase current on Vccq rail (e.g. NAND Iccq3 specification) in mA

結果

System Workload breakout per host NAND channel

Most used Read Operation %

Most used Program Operation %

% of time a NAND die is in Idle state

2nd most used Read Operation %

Most used Erase Operation %

% of time a NAND die is in Standby state

Total NAND Power per host channel (in W)
Must add up to 100%

Total NAND Power for all host channels (in W) Learn More
Must add up to 100%

Values for NAND LUNs/die busy with most used Read Operation

NAND system current per channel (in mA)

NAND system power per channel (in W)

NAND Vcc power rail during NAND array operations

NAND Vccq power rail during NAND array operations

NAND Vcc power rail during data output

NAND Vccq power rail during data output Learn More

NAND Vpp power rail during array operations (if used)

Values for NAND LUNs/die busy with 2nd most used Read operation

NAND system current per channel (in mA)

NAND system power per channel (in W)

NAND Vcc power rail during NAND array operations

NAND Vccq power rail during NAND array operations

NAND Vcc power rail during data output

NAND Vccq power rail during data output Learn More

NAND Vpp power rail during array operations (if used)

Values for NAND LUNs/die busy with most used Program operation

NAND system current per channel (in mA)

NAND system power per channel (in W)

NAND Vcc power rail during NAND array operations

NAND Vccq power rail during NAND array operations

NAND Vcc power rail during data input

NAND Vccq power rail during data input

NAND Vpp power rail during array operations (if used)

Values for NAND LUNs/die busy with most used Erase operation

NAND system current per channel (in mA)

NAND system power per channel (in W)

NAND Vcc power rail during NAND array operations

NAND Vccq power rail during NAND array operations

NAND Vpp power rail during array operations (if used)