35.2 milliseconds to market insight

A record-setting STAC-A2 run showcases the importance of compute-memory alignment in financial modeling.

What is true about memory in financial infrastructure

Memory has always played a role in financial systems, but it has long been treated as part of the supporting cast. A reliable place to hold data, not shape decisions. Part of the general reason for that is that memory performance improvements have been incremental and under-publicized.¹ Many financial workloads were tuned to CPU performance and storage, with less visibility into memory bandwidth as a bottleneck until recently.² But that view is changing. Memory has always been foundational, but now system architects are designing with a deeper understanding of how compute and memory must work together. That shift is showing up clearly in financial modeling and HPC systems, where thousands of simulations run side by side and data must move fast enough to keep pace with the model's logic. No single component defines the system behavior. What matters is how well compute and memory are tuned to meet each other, and whether the architect can shape that interplay across the full stack. In that design, memory plays a distinct role: it sets the pace for how data flows and how cleanly that data moves across the system.

In the hands of an HPC architect building risk engines, memory is no longer just part of the stack; it's a lever that determines how far and how fast the system can model financial outcomes. These systems are shaped by people who build at the intersection of hardware and financial markets, and these teams who must constantly ask:

What can we architect (at the system level) so we're ready before the market moves?

This blog draws on the recent world record STAC-A2 result not as the headline, but as a lens: a way to show what becomes possible when memory and compute are tuned to meet each other. This result, achieved by a system configured with Intel^® Xeon^® 6 processors and Micron 8800 MT/s MRDIMMs (Multiplexed Rank DIMMs), didn't happen by accident. It came from intentional design: Micron and Intel working closely together to align memory and compute architecture at the system level.

That kind of alignment goes beyond design philosophy; it proves itself under real workload pressure. One way to see it clearly is through the STAC-A2 benchmark: a test designed to push modeling systems to their edge by simulating how financial instruments might behave, day by day, across thousands of market scenarios. What follows is a closer look at what the benchmark asks of a system and how it brings into focus the kind of sustained memory throughput and system-level coordination required to keep pace as that demand scales.

Inside the STAC-A2 benchmark

The STAC-A2 benchmark asks a platform to do something quite demanding: simulate thousands of financial scenarios at the same time. Those scenarios are built from something called simulated price paths — models of how a financial instrument, like a multi-asset option, might behave over time as markets rise, fall or move sideways. It's a stress test not just for compute, but also for memory.

A typical run models thousands of price paths, each one stepping through 252 time intervals. The number 252 isn’t arbitrary. It maps to the number of trading days in a typical calendar year. So, when we say this benchmark stimulates thousands of outcomes across 252 “timesteps,” we're describing a system that models day-by-day market behavior across a full trading year for 25,000 different financial scenarios.³ That means thousands of calculations unfolding side by side, demanding consistent performance from every core, but also memory bandwidth pushed to its limit, as threads continuously, read from and write to shared memory throughout the simulation. And in the end, the system can only move as fast as its memory allows.